IA-64: A Parallel Instruction Set: 5/31/99

Finally allowing a full evaluation of their new instruction set, Intel and Hewlett-Packard have released a full description of IA-64’s application-level architecture and instruction set. The disclosures address some previous criticisms of the architecture and provide more details concerning how IA-64 processors will execute both x86 and PA-RISC binaries. The disclosures show a thoroughly modern instruction set with a range of multimedia instructions and prefetch capabilities. Although IA-64 includes many RISC concepts, the architects added some rather complicated and specialized instructions. Concerns remain, however, about code density and just how much of an advantage these new features will provide over a standard RISC architecture. One criticism had been that the large register file, while effective for compute-intensive routines, would cause excessive overhead on subroutine calls, due to saving and restoring the contents of the registers. The vendors disclosed that IA-64 supports register frames that alleviate much of call/ save overhead.